1. Technical Field
Exemplary embodiments described herein relate to a complementary MIS semiconductor device whose gate electrode structure is improved.
2. Description of the Related Art
In recent years, in silicon complementary metal-insulator-semiconductor (CMIS) semiconductor devices, use of a high-melting-point metal such as titanium, molybdenum, tungsten and tantalum, or a nitride thereof as a gate electrode has been attempted, which is referred to as the metal gate technique.
With the metal gate technique, since a depletion layer is not generated in a gate electrode in principle, current drive performance of an MIS transistor is not reduced by the depletion layer, unlike conventional polysilicon gates. Particularly, in a so-called single metal gate technique where both gate electrodes of an n-channel MIS transistor and a p-channel MIS transistor consist of a single metal gate material, deposition and patterning of the gate electrodes can be performed at the same time for the n-channel MIS transistor and the p-channel MIS transistor. As a result, problems such as complication and an increase in process steps, which arise when using different metal gates for the n-channel MIS transistor and the p-channel MIS transistor, can be solved.
An example of the single metal gate technique is a technique such that both gate electrodes of the n-channel and p-channel MIS transistors are formed by an alloy of Ta and C, and a composition of the TaC alloy is controlled so that a mole ratio of Ta to a total of Ta and C, (Ta/(Ta+C)), becomes ⅓ or less to ⅕ or more (see JP-A 2007-149755 (KOKAI)). A TaxC1-x electrode having the composition in this range is stable even at the time of a heat treatment at 1000° C., and shows a work function within a range of 4.5 to 4.7 eV.
On the other hand, in a dual metal gate technique using the alloy including Ta and C, such a technique that realizes the dual work functions suitable for the p-channel and n-channel MIS transistors by optimizing a crystal orientation ratio of TaC (111) faces, is known (see JP-A 2007-165414 (KOKAI)). In this technique, the crystal orientation ratio of the TaC (111) face of the p-channel MIS transistor is set to 80% or more, and the crystal orientation ratio of the TaC (111) face of the n-channel MIS transistor is set to 60% or less. A ratio of C to Ta, C/Ta, is defined within a range of 0.5 or more to 1.5 or less.
In such MIS transistors having a metal gate electrode, however, a reduction of inversion layer carrier mobility due to the metal gate electrode frequently becomes a problem. For this reason, a metal gate technique which maintains high mobility is required, but a method for realizing this is not known.
In order to improve the current drive performance of transistors and realize silicon CMIS (or CMOS) devices with high processing speed, it is indispensable to introduce the metal gate technique instead of the conventional polysilicon gate. However, a single metal gate structure which represses the reduction in the inversion layer carrier mobility to the minimum is not currently realized.
For this reason, it has been desired that semiconductor devices, which have a single metal gate structure suitable for silicon CMIS devices or the like and particularly can maintain high inversion layer carrier mobility, can be realized.